Log file created by Broadcom NetXtreme/NetLink Engineering Diagnostics 14.63 on: Sun Mar 27 11:49:47 2011 --------------------------------------------- ***************************************************************** Copyright(c) 2000-2011 Broadcom Corporation, all rights reserved. Broadcom NetXtreme/NetLink Engineering Diagnostics 14.63 (02/01/11) ***************************************************************** C Brd Rv Bus PCI Spd Base Irq NVM(avl/max) MAC Boot Code Config - -------- ------- --- --- ---- -- ---------- ------------ ----------- ------- 0 57781:B0 0B:00:0 Ex1 250 D001 5 64k/ 64k 002522000036 sb2 2.05 LPh 0:>semode Current mode: New NVRAM Access, Auto device: OTP , Enc=0 0:>secfg SB_II Aspen Configuration Menu 1. MAC Address...........(1/4): 002522000036 2. Sub Vendor Id.........(1/4): 1849 3. Sub Device Id Func_0..(0/4): 96B1 7. Wake on LAN...........(0/4): Disabled 8. WoL Speed Limit 10....(0/2): Disabled 9. LOM/NIC design........(0/2): LOM a. Phy. Auto PowerDown...(0/2): Enabled b. LED mode..............(1/4): PHY 2 (PHY) Mode x. Save & exit. Esc to ignore any change. -> e SB_II Aspen Configuration Menu 1. MAC Address...........(1/4): 002522000036 2. Sub Vendor Id.........(1/4): 1849 3. Sub Device Id Func_0..(0/4): 96B1 7. Wake on LAN...........(0/4): Disabled 8. WoL Speed Limit 10....(0/2): Disabled 9. LOM/NIC design........(0/2): LOM a. Phy. Auto PowerDown...(0/2): Enabled b. LED mode..............(1/4): PHY 2 (PHY) Mode x. Save & exit. Esc to ignore any change. -> a SB_II Aspen Configuration Menu 1. MAC Address...........(1/4): 002522000036 2. Sub Vendor Id.........(1/4): 1849 3. Sub Device Id Func_0..(0/4): 96B1 7. Wake on LAN...........(0/4): Disabled 8. WoL Speed Limit 10....(0/2): Disabled 9. LOM/NIC design........(0/2): LOM a. Phy. Auto PowerDown...(0/2): Disabled b. LED mode..............(1/4): PHY 2 (PHY) Mode x. Save & exit. Esc to ignore any change. -> d SB_II Aspen Configuration Menu 1. MAC Address...........(1/4): 002522000036 2. Sub Vendor Id.........(1/4): 1849 3. Sub Device Id Func_0..(0/4): 96B1 7. Wake on LAN...........(0/4): Disabled 8. WoL Speed Limit 10....(0/2): Disabled 9. LOM/NIC design........(0/2): LOM a. Phy. Auto PowerDown...(0/2): Disabled b. LED mode..............(1/4): PHY 2 (PHY) Mode x. Save & exit. Esc to ignore any change. -> x Disable phy_auto_power_down Data saved to OTP 0:>semode Current mode: New NVRAM Access, Auto device: OTP , Enc=0 0:>secfg SB_II Aspen Configuration Menu 1. MAC Address...........(1/4): 002522000036 2. Sub Vendor Id.........(1/4): 1849 3. Sub Device Id Func_0..(0/4): 96B1 7. Wake on LAN...........(0/4): Disabled 8. WoL Speed Limit 10....(0/2): Disabled 9. LOM/NIC design........(0/2): LOM a. Phy. Auto PowerDown...(1/2): Disabled b. LED mode..............(1/4): PHY 2 (PHY) Mode x. Save & exit. Esc to ignore any change. -> Exit without changing data 0:>read o0 100 00000000: 00000000 00000000 0000152a 40000000 00000010: 00001024 16b10000 00000000 00000000 00000020: a0000000 00000005 00000025 00000000 00000030: 22000036 00000000 00000000 00000000 00000040: 00001900 00400000 10000000 00001849 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00000000 00000000 00000070: 00000000 72800600 c3e86800 c6107c0c 00000080: ff804040 c4e86800 c630006c fffffc7f 00000090: 32800288 081f8010 08190064 128002a8 000000A0: c4e03600 c40864c0 7600449c ce800400 000000B0: 0101000c 04780c10 03780c10 00000000 000000C0: 00000000 00000000 00000000 00000000 000000D0: 00000000 00000000 00000000 00000000 000000E0: 00000000 00000000 00000000 00000000 000000F0: 00000000 00000000 00000000 00000000 0:>otpchk Current Minor Rev = 5 Num CPD Len Active Code Override Type ECC TOA Result --- -------- --- ------ ---- -------- ---- --- --- ------- 0 72800600 6 Yes ICP No SBPI 1CA 6 PASS 17 32800288 2 Yes ICP No SBPI CA 6 PASS 19 7600449C 4 Yes SCP No SBPI 1D8 6 PASS 21 128002A8 2 Yes ICP No SBPI 4A 6 PASS 0:>verbose -idf 0. Exit 1. Console....:yes 2. Error......:yes 3. IO.........:yes 4. DEBUG......:yes 5. PRINTER....:no 6. WARNING....:yes 7. Interrupt..:no 8. Flush......:yes 9. Hidden IO..:no a. IPSEC Trace:no Type "Help" for command list code=0 0:>seprg -f otp1466.bin tcl_cmd_executeString:seprg -f otp1466.bin firstOpt(2):argu[0]=seprg argu[1]=-f argu[2]=otp1466.bin func_seprg: File Name : otp1466.bin File Size : 112 Offset : 0x0000 Bytes Read : 112 Checking selfboot file Content........: sb_chksum_all_rev, rev=5, chksum=0.passed ValidateFileDeviceId : ver = 00020500 Image ID = 16b1, Mpart, board ID = 16b1, Mpart, reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000100 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> a0000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0020) : a0000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000120 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008f reg rd: 0x7514 --> 00000005 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0024) : 00000005 reg rd: 0x7508 --> 0000008f reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000140 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008f reg rd: 0x7514 --> 00000025 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0028) : 00000025 reg rd: 0x7508 --> 0000008f reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000160 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(002c) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000180 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 22000036 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0030) : 22000036 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000001a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0034) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000001c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0038) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000001e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(003c) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000200 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00001900 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0040) : 00001900 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000220 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00400000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0044) : 00400000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000240 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 10000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0048) : 10000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000260 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008f reg rd: 0x7514 --> 00001849 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(004c) : 00001849 reg rd: 0x7508 --> 0000008f reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000280 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0050) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000002a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0054) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000002c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0058) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000002e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(005c) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000300 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0060) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000320 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0064) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000340 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0068) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000360 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(006c) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000380 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0070) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000003a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 72800600 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0074) : 72800600 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000003c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c3e86800 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0078) : c3e86800 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000003e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c6107c0c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(007c) : c6107c0c reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000400 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> ff804040 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0080) : ff804040 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000420 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c4e86800 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0084) : c4e86800 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000440 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c630006c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0088) : c630006c reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000460 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008f reg rd: 0x7514 --> fffffc7f reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(008c) : fffffc7f reg rd: 0x7508 --> 0000008f reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000480 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 32800288 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0090) : 32800288 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000004a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 081f8010 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0094) : 081f8010 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000004c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 08190064 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(0098) : 08190064 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000004e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 128002a8 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(009c) : 128002a8 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000500 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c4e03600 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00a0) : c4e03600 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000520 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c40864c0 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00a4) : c40864c0 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000540 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 7600449c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00a8) : 7600449c reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000560 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> ce800400 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00ac) : ce800400 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000580 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 0101000c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00b0) : 0101000c reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000005a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 04780c10 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00b4) : 04780c10 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000005c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 03780c10 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00b8) : 03780c10 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000005e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00bc) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000600 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00c0) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000620 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00c4) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000640 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00c8) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000660 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00cc) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000680 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00d0) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000006a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00d4) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000006c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00d8) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000006e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00dc) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000700 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00e0) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000720 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00e4) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000740 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00e8) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000760 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00ec) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000780 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00f0) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000007a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00f4) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000007c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00f8) : 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000007e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 00000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 otp_load32(00fc) : 00000000 asp_otp_VerifyContent in: ignorError=1, ckFile=0: Checking Aspen SB OTP Content.........: asp otp cfg = a0000000 Verify CPD(0)=72800600 Verify CPD(17)=32800288 Verify CPD(21)=128002a8 Verify CPD(19)=7600449c Verify CPD(0)=0 asp_otp_VerifyContent < : 0 passed Restoring original configuration settings in OTP. Restoring original MAC address 002522000036 sb_chksum_all_rev, rev=5, chksum=fc. Translating SB to Aspen OTP..... format = 1, revision = 5 Enable WOL EnablegenECC: chkout=1ca CPD=72800600,ecc=1ca,patch=c3e86800 c6107c0c ff804040 c4e86800 c630006c fffffc7f genECC: chkout=ca CPD=32800288,ecc=ca,patch=081f8010 08190064 genECC: chkout=4a CPD=128002a8,ecc=4a,patch=c4e03600 c40864c0 SCP Header = 59402010 Patch#: 19, CPD: 9810 Type: SBPI, Override: No, Length: 0x10 genECC: chkout=1d8 CPD=7600449c,ecc=1d8,patch=ce800400 101000c 4780c10 3780c10 Translated 4 patches, minor revision = 5 asp_otp_VerifyContent in: ignorError=0, ckFile=1: Checking Aspen SB file Content........: asp otp cfg = a0000000 Verify CPD(0)=72800600 Verify CPD(17)=32800288 Verify CPD(21)=128002a8 Verify CPD(19)=7600449c Verify CPD(0)=0 asp_otp_VerifyContent < : 0 passed Programming to OTP ... asp_otp_saveImage:keepOriginalCfg=1 asp_Synthesize :> Header part asp_otp_get_minorRev: Ver_I=0, Ver_II=5 pos=1,v=5,obsolete_idx=0 asp_otp_get_minorRev: Ver_I=0, Ver_II=5 pos=1,v=5,obsolete_idx=0 asp_getCfg : mac = 002522000036 asp_getCfg : did0 = 16b1 asp_getCfg : did1 = 16bc asp_getCfg : ssid0(1) = 96b1 asp_getCfg : ssid1(1) = 96bc asp_getCfg : ssid2(1) = 96be asp_getCfg : ssid3(1) = 96bf asp_getCfg : svid(1) = 1849 asp_saveCfg:MAC MAC(1)=002522000036 in OTP MAC =002522000036 in ASPCFG asp_saveCfg:ssid fun0 asp_saveCfg:ssid fun1 asp_saveCfg:ssid fun2 asp_saveCfg:ssid fun3 asp_saveCfg:svid asp_saveCfg:confign Enable phy_auto_power_down Enable wol_enable asp_saveCfg:ret=0 Patch part asp_otp_patchSize : pcnt=0x4, bsize=0x48. patch_len=48,patch_cnt=4 in OTP asp_otp_patchSize : pcnt=0x4, bsize=0x48. patch_len=48,patch_cnt=4 in Image Go to the first free DW at 9c Src.ecc=1ca;Dest.ecc=1ca Rule1 .Src.ecc=ca;Dest.ecc=ca Rule1 .Src.ecc=4a;Dest.ecc=4a Rule1 .Src.ecc=1d8;Dest.ecc=1d8 Rule1 . asp_otp_patchSize : pcnt=0x4, bsize=0x48. Start to program image into OTP ... Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000100 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> a0000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000100 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> a0000000 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000120 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008f reg rd: 0x7514 --> 00000005 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 CPD=72800600 written to 74,Read and check data reg rd: 0x7508 --> 0000008f reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000003a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 72800600 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000003a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 72800600 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 read back => 72800600. Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000003c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c3e86800 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000003e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c6107c0c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000400 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> ff804040 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000420 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c4e86800 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000440 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c630006c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000460 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008f reg rd: 0x7514 --> fffffc7f reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 CPD=32800288 written to 90,Read and check data reg rd: 0x7508 --> 0000008f reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000480 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 32800288 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000480 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 32800288 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 read back => 32800288. Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000004a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 081f8010 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000004c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 08190064 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 CPD=128002a8 written to 9c,Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000004e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 128002a8 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000004e0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 128002a8 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 read back => 128002a8. Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000500 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c4e03600 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000520 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> c40864c0 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 CPD=7600449c written to a8,Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000540 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 7600449c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000540 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 7600449c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 read back => 7600449c. Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000560 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> ce800400 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 00000580 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 0101000c reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000005a0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 04780c10 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 Read and check data reg rd: 0x7508 --> 0000008b reg wr: 0x7518 <-- 00000001 reg wr: 0x7518 <-- 00000000 reg wr: 0x7500 <-- 00000001 reg wr: 0x750c <-- 000005c0 reg wr: 0x7504 <-- 00000000 reg rd: 0x7504 --> 00000000 reg wr: 0x7504 <-- 00000001 reg rd: 0x7504 --> 00000001 reg rd: 0x7508 --> 0000008b reg rd: 0x7514 --> 03780c10 reg wr: 0x7500 <-- 00000000 reg wr: 0x7504 <-- 00000000 reg wr: 0x750c <-- 00000000 reg wr: 0x7510 <-- 00000000 156 bytes was done. Type "Help" for command list code=0 0:>verbose -idf tcl_cmd_executeString:verbose -idf firstOpt(1):argu[0]=verbose argu[1]=-idf 0. Exit 1. Console....:yes 2. Error......:yes 3. IO.........:no 4. DEBUG......:no 5. PRINTER....:no 6. WARNING....:yes 7. Interrupt..:no 8. Flush......:no 9. Hidden IO..:no a. IPSEC Trace:no 0:>read 0 o0 100 00000000: 00000000 00000000 0000152a 40000000 00000010: 00001024 16b10000 00000000 00000000 00000020: a0000000 00000005 00000025 00000000 00000030: 22000036 00000000 00000000 00000000 00000040: 00001900 00400000 10000000 00001849 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00000000 00000000 00000070: 00000000 72800600 c3e86800 c6107c0c 00000080: ff804040 c4e86800 c630006c fffffc7f 00000090: 32800288 081f8010 08190064 128002a8 000000A0: c4e03600 c40864c0 7600449c ce800400 000000B0: 0101000c 04780c10 03780c10 00000000 000000C0: 00000000 00000000 00000000 00000000 000000D0: 00000000 00000000 00000000 00000000 000000E0: 00000000 00000000 00000000 00000000 000000F0: 00000000 00000000 00000000 00000000 0:>otpchj k Current Minor Rev = 5 Num CPD Len Active Code Override Type ECC TOA Result --- -------- --- ------ ---- -------- ---- --- --- ------- 0 72800600 6 Yes ICP No SBPI 1CA 6 PASS 17 32800288 2 Yes ICP No SBPI CA 6 PASS 19 7600449C 4 Yes SCP No SBPI 1D8 6 PASS 21 128002A8 2 Yes ICP No SBPI 4A 6 PASS 0:>exit